In-pixel analog memories for a pixel-based background subtraction algorithm on CMOS vision sensors

This paper addresses the most suitable in-pixel analog memory bank for running a hardware-oriented approach of the well-known Pixel-Based Adaptive Segmenter algorithm on CMOS vision sensors. The high number of memory accesses, typically up to 200 times, along with the long time elapsed before an analog memory in a pixel is updated, around 5 seconds at 30 fps, constrains the memory topology. This work assesses the impact of nominal and process nonidealities of the 3 main analog memory topologies, namely, open-loop, closed-loop, and integrator architectures for background subtraction over the CDNET14 database. This is the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the Pixel-Based Adaptive Segmenter.