Codesign toolset for application-specific instruction-set processors

Application-specific programmable processors tailored for the requirements at hand are often at the center of today's embedded systems. Therefore, it is not surprising that considerable effort has been spent on constructing tools that assist in codesigning application-specific processors for embedded systems. It is desirable that such design toolsets support an automated design flow from application source code down to synthesizable processor description and optimized machine code. In this paper, such a toolset is described. The toolset is based on a customizable processor architecture template, which is VLIW-derived architecture paradigm called Transport Triggered Architecture (TTA). The toolset addresses some of the pressing shortcomings found in existing toolsets, such as lack of automated exploration of the "design space", limited run time retargetability of the design tools or restrictions in the customization of the target processors.