A 2.5 Gbps-3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOS

被引：6
|
作者：
Geurts, T [1 ]
Rens, W [1 ]
Crols, J [1 ]
Kashiwakura, S [1 ]
Segawa, Y [1 ]
机构：
[1] AnSem, B-3001 Heverlee, Belgium
来源：
ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2004年
关键词：
D O I：
10.1109/ESSCIR.2004.1356725
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A multi-rate serdes macro that is targeting multi-channel applications has been developed in 0.13 mum. A low jitter LC VCO PLL can provide the master clock for up to 16 receive and transmit modules. Specific provisions for operation at different data rates are present. The receive module operates at full rate. Comma detection and 8b/10b coding are present. The transmitter has a measured output jitter of 8.1 ps rms at 2.5 Gbps. The receiver has a measured intrinsic jitter tolerance of 0.75 UI. Power consumption for the PLL is 40 mW, a receive and transmit pair consumers 100 mW.
引用
收藏
页码：487 / 490
页数：4
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