An novel low power embedded memory architecture for MPEG-4 applications with mobile devices

被引：0

作者：

Sayed, M ^{[1
]}

Badawy, W ^{[1
]}

机构：

[1] Univ Calgary, Dept Elect & Comp Engn, Calgary, AB T2N 1N4, Canada

来源：

SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS | 2003年

关键词：

system on chip; embedded memory; digital video processing; MPEG-4; applications;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a novel embedded memory architecture for MPEG-4 synthetic video object decoding that is used in a new chipset for third generation mobile phones. The embedded memory architecture stores video frame and motion vectors, then it computes in memory the predicted frame, which generates the MPEG-4 video sequence. The embedded memory is optimized with a parallel reading and writing operations. The architecture has been prototyped in 0.35 i m CMOS technology using TSMC standard cells and the Digital Video Processing and Digital VLSI Prototyping (DVP(2)) group's custom cells.

引用

页码：262 / 272

页数：11

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