Single chip implementation of encoder-decoder for low bit rate visual communication

A single chip encoder-decoder dedicated to low bit rate visual communication is proposed, with the main theme focused on the object extraction and vector quantization. New schemes are introduced into an edge detector so as to extract objects by means of the block-level edge detection in conjunction with the pel-level edge detection and into a PE (Processing Element) array so as to be shared by the vector quantizer and the motion estimator. Owing to sophisticated architectures, these CODEC facilities have been implemented in 72.24 mm(2) by a 0.6 mu m triple-metal CMOS technology, which can enable the visual communication of QCIF (176 x 144) 10 fps pictures at a bit rate of 32 Kbps or less. The designed encoder-decoder operates at 10 MHz, and dissipates 147 mW from a single 3.3 V supply.