Strain induced changes in performance of strained-Si/strained-Si1-y Ge y /relaxed-Si1-x Ge x MOSFETs and circuits for digital applications

Growing a silicon (Si) layer on top of stacked Si-germanium (Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor (CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors (MOSFETs) into the deep submicron/nanometer regime forces the source (S) and drain (D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si1-y Ge (y) /relaxed-Si1-x Ge (x) MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.