Ultrafast Characterization of Hole Trapping Near Black Phosphorus-SiO2 Interface During NBTI Stress in 2-D BP p-FETs

被引：4

作者：

Goyal, Natasha ^{[1
]}

Mahapatra, Souvik ^{[1
]}

Lodha, Saurabh ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Mumbai 400076, Maharashtra, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2019年 / 66卷 / 11期

关键词：

Stress; Time measurement; Negative bias temperature instability; Thermal variables control; Voltage measurement; Stress measurement; Logic gates; 2-D p-FET; black phosphorus (BP); hole trapping; negative bias temperature instability (NBTI); ultrafast measurement; FIELD-EFFECT TRANSISTORS; PHOSPHORENE; BULK;

D O I：

10.1109/TED.2019.2943180

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

2-D p-channel FETs with black phosphorus (BP) channel and silicon dioxide (SiO2) gate oxide have been fabricated. An ultrafast characterization method (10-mu s delay) is used to measure the shift in threshold voltage (V-T) during and after negative bias temperature instability (NBTI) stress under different gate biases (V-GSTR) and temperatures (T). The V-T stress and recovery kinetics are ascribed to hole trapping and detrapping (V-HT) near the BP-SiO2 interface, due to the choice of channel material, SiO2 thickness (TOX), and stress (V-GSTR /T) conditions. A detailed analysis is done to determine the projected magnitude of V-T without any delay, for different V-GSTR and T, and at thinner TOX relevant for realistic end-use cases.

引用

页码：4572 / 4577

页数：6