Experience with applying formal methods to protocol specification and system architecture

被引：2

作者：

Azimi, M ^{[1
]}

Chou, CT ^{[1
]}

Kumar, A ^{[1
]}

Lee, VW ^{[1
]}

Mannava, PK ^{[1
]}

Park, S ^{[1
]}

机构：

[1] Intel Corp, Santa Clara, CA 95054 USA

来源：

FORMAL METHODS IN SYSTEM DESIGN | 2003年 / 22卷 / 02期

关键词：

formal verification; cache coherence protocols; sliding window protocols; rule-based checking of tables; minimal deadlock-free wormhole routing schemes; fault-tolerant link initialization;

D O I：

10.1023/A:1022965204416

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In the last three years or so we at Enterprise Platforms Group at Intel Corporation have been applying formal methods to various problems that arose during the process of defining platform architectures for Intel's processor families. In this paper we give an overview of some of the problems we have worked on, the results we have obtained, and the lessons we have learned. The last topic is addressed mainly from the perspective of platform architects.

引用

页码：109 / 116

页数：8

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