FPGA implementation of space-time block coding systems

被引：5
|
作者：
Baghaie, M [1 ]
Kuo, S [1 ]
McLoughlin, IV [1 ]
机构：
[1] Univ Canterbury, Dept Elect & Comp Engn, Christchurch 1, New Zealand
来源：
PROCEEDINGS OF THE IEEE 6TH CIRCUITS AND SYSTEMS SYMPOSIUM ON EMERGING TECHNOLOGIES: FRONTIERS OF MOBILE AND WIRELESS COMMUNICATION, VOLS 1 AND 2 | 2004年
关键词：
space-time processing; space-time block coding; time-reversal; programmable logic; FPGA; wireless channels;
D O I：
10.1109/CASSET.2004.1321957
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, the implementation of space-time block coding systems is discussed, particularly through the use of programmable logic such as FPGAs. The rationale for choice of such devices in preference to DSPs is discussed followed by an analysis of the design and development process and the methodologies employed in the design process. An example space-time system, time-reversal space-time block coding (TR-STBC) is discussed and implementation described.
引用
收藏
页码：591 / 594
页数：4
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