A reconfigurable analog-to-digital converter for UTRA-TDD mobile terminal receiver

被引：0
|
作者：
Stojcevski, A [1 ]
Singh, J [1 ]
Zayegh, A [1 ]
机构：
[1] Victoria Univ, Ctr Telecommun & Microelect, Melbourne, Vic 8001, Australia
来源：
2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A reconfigurable analog-to-digital converter (ADC) has been proposed for a mobile terminal. This architecture scales the digital word length (bits) by automatically monitoring desired power and adjacent channel interference power. This leads to power consumption savings, depending on the number of bits used. The architecture can scale between a minimum of 4 bits and maximum of 16 bits. The new reconfigurable ADC was applied to Time-Division-Duplex (TDD) mode of UNITS Terrestrial Radio Access (UTRA) system and results show that this reconfigurable ADC can save up 75 % of the power consumption when compared with the power consumption of a standard 16-bit analog-to-digital converter.
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页码：613 / 616
页数：4
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