A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS

被引：3

作者：

Edler, Julius ^{[1
]}

Runge, Marcel ^{[1
]}

Gerfers, Friedel ^{[1
]}

机构：

[1] Tech Univ Berlin, Chair Mixed Signal Circuit Design, Berlin, Germany

来源：

2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS) | 2021年

关键词：

ADC; sigma-delta; GmC; linearization; body-bias; FD-SOI; silicon-on-insulator; back-bias amplification; Analog integrated circuits; Feedback; Active Filters; MODULATOR;

D O I：

10.1109/MWSCAS47672.2021.9531807

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a linearization technique for differential transconductors in fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Dynamic self-biasing is employed at the back-gate node thereby compensating the non-linearity of the main differential input pair. The method yields excellent linearity beyond 85 dBc under a considerable input voltage 1 Vppd and is highly applicable in high-bandwidth and wide-swing GmC based Sigma-Delta converters. The basic principle of the linearization is introduced and proven in a complex ADC architecture. Transistor level simulations show a linearity improvement of 25 dB while only increasing the loop filters power dissipation by 10 %. Process corner, temperature as well as mismatch dependency is evaluated proving the concepts robustness and efficiency.

引用

页码：1090 / 1093

页数：4