Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (V-GS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative V-GS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (V-TH) shift, on-state resistance (RDS-ON) increase, transconductance max (G(m, max)) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative V-GS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the V-TH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.