Real-time deblocking filter for MPEG-4 systems

被引：0
|
作者：
Fang, HC [1 ]
Wang, TC [1 ]
Chen, LG [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan
来源：
APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a deblocking filter architecture in MPEG-4 standard. This architecture performs 1-D nonlinear filter across block boundary to efficiently suppress blocking artifacts. Two shift register banks are used in the design. The use of them greatly reduces the control complexity of data flow. Due to efficient scheduling, the size of storage and the total clock cycles are minimized. The maximum processing rate of this architecture mapped in 0.35 mum technology is 30 M pixels/sec, which can support NTSC resolution at 30 frames per second. The power consumption of the design is 46.6 mW while operating frequency is 81 Mhz.
引用
收藏
页码：541 / 544
页数：4
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