A 180nm copper/Low-k CMOS technology with dual gate oxide optimized for low power and low cost consumer wireless applications

被引：7

作者：

Yeap, GCF ^{[1
]}

Nkansah, F ^{[1
]}

Chen, J ^{[1
]}

Jallepalli, S ^{[1
]}

Pham, D ^{[1
]}

Lii, T ^{[1
]}

Nangia, A ^{[1
]}

Le, P ^{[1
]}

Hall, D ^{[1
]}

Menke, D ^{[1
]}

Sun, J ^{[1
]}

Das, A ^{[1
]}

Gilbert, P ^{[1
]}

Huang, F ^{[1
]}

Sturtevant, J ^{[1
]}

Green, K ^{[1
]}

Lu, J ^{[1
]}

Benavidas, J ^{[1
]}

Bankds, E ^{[1
]}

Chung, J ^{[1
]}

Lage, C ^{[1
]}

机构：

[1] Motorola Inc, Digital DNA Labs, Austin, TX 78721 USA

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852805

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We report a 180nm CMOS technology with dual gate oxide (DGO) optimized for low power and low cost consumer wireless products. To minimize cost and maximize manufacturability, super halo is used for the first time to integrate 70 Angstrom 2.5-3.3V I/O devices with either 130nm/29 Angstrom or 150nm/35 Angstrom low leakage (LL) p Angstrom/mu m devices, eliminating three normally-required masks. Core LL devices optimized for 1.5V and 1.8V are available to maximize circuit design compatibility and IP reuse. Both LL devices yield superior performance, and less I-on/I-off sensitivity vs, gate-length control for robust manufacturing as compared to recently reported U devices (see Table. 1). This technology also features an all-layer copper/low-k interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction [1].

引用

页码：150 / 151

页数：2

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