New clock-gating techniques for low-power flip-flops

被引：30

作者：

Strollo, AGM ^{[1
]}

Napoli, E ^{[1
]}

De Caro, D ^{[1
]}

机构：

[1] Univ Naples Federico II, Dept Elect & Telecommun Engn, Naples, Italy

来源：

ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2000年

关键词：

CMOS digital integrated circuits; flip-fops; low-power circuits; transition probability;

D O I：

10.1109/LPE.2000.876767

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle Limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.

引用

页码：114 / 119

页数：6

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