A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector

被引：18

作者：

Jin, Jahoon ^{[1
]}

Jin, Xuefan ^{[1
]}

Jung, Jaehong ^{[1
,2
]}

Kwon, Kiwon ^{[1
,2
]}

Kim, Jintae ^{[3
]}

Chun, Jung-Hoon ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 16419, South Korea

[2] Samsung Elect, Hwaseong 18448, South Korea

[3] Konkuk Univ, Dept Elect Engn, Seoul 05029, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2018年 / 53卷 / 10期

关键词：

Clock and data recovery (CDR); deadzone compensation; dual-mode; frequency acquisition; jitter tolerance (JTOL); referenceless; temperature compensation; DATA RECOVERY CIRCUIT; ADAPTIVE EQUALIZATION; SUBTHRESHOLD MOSFETS; CMOS; ACQUISITION; CLOCK; TRANSCEIVER; PHASE; PLL;

D O I：

10.1109/JSSC.2018.2856243

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10(-)(12) over a wide temperature range from -20 degrees C to 120 degrees C.

引用

页码：2994 / 3003

页数：10