A Low-Power Wide-Band Digital Frequency Synthesizer for Cognitive Radio Sensor Units

被引:0
|
作者
Xu, Liangge [1 ]
Stadius, Kari [1 ]
Ryynanen, Jussi [1 ]
机构
[1] Helsinki Univ Technol, Dept Micro & Nanosci SMARAD 2, FIN-02150 Espoo, Finland
关键词
PLL; CMOS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the design of a wide-band digital frequency synthesizer for cognitive radio sensor units. It is based on an all-digital phase-locked loop, and employs a digitally controlled ring oscillator with an LC tank introduced to extend tuning range and reduce power dissipation. Adaptive frequency calibration based on binary search is used for fast frequency settling. Fabricated in a 65-nm CMOS, the frequency synthesizer has an active area of 0.3 mm(2) and achieves a frequency tuning range of 2.7 to 6.1 GHz, with power consumption less than 22 mW from a 1.2-V supply. Measured phase noise at 6-GHz frequency is 92 dBc/Hz at 1-MHz offset.
引用
收藏
页码:185 / 188
页数:4
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