A JPEG chip for image compression and decompression

JPEG is an international standard for still-image compression/decompression and has been widely implemented in hardware. In this paper, we describe the development of a JPEG chip which employs a single-chip implementation and an efficient architecture of Huffman codec. Firstly, we use VHDL (VHSIC Hardware Description Language) to describe the behavior of the chip. Each functional block of the chip is defined and simulated. An architecture consisting of two RAMs is adopted to reduce the size of the Huffman tables. Then we verify the functionality of our design with field programmable gate arrays (FPGAs) on circuit boards. Finally, a single chip is implemented using the standard cell design approach with the 0.6 mu triple-metal process. The chip is compliant with the JPEG baseline system and can work in real time at any compression ratio. The chip contains 2 411,745 transistors, with a chip size of 6.6 x 6.9 mm(2).