Improving Data Cache Performance using Persistence Selective Caching

被引:0
|
作者
Kumar, Sumeet S. [1 ]
van Leuken, Rene [1 ]
机构
[1] Delft Univ Technol, Fac EEMCS, Circuits & Syst Grp, NL-2600 AA Delft, Netherlands
关键词
cache memory; memory architecture; memory management; microprocessors;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents Persistence Selective Caching (PSC), a selective caching scheme that tracks the reusability of L1 data cache (L1D) lines at runtime, and moves lines with sufficient potential for reuse to a low-latency, low-energy assist cache from where subsequent references to them are serviced. The selectivity of PSC is configurable, and can be adjusted to suit the varying memory access characteristics of different applications, unlike existing schemes. By effectively identifying reusable cache lines and storing them in the assist, PSC reduces average memory access time by upto 59% as compared to competing schemes and conventional data caches. Furthermore, by ensuring that only reusable lines are cached by the assist, PSC reduces cache line movements, and thus decreases average energy per access by upto 75% over other assists.
引用
收藏
页码:1945 / 1948
页数:4
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