A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges

This brief presents an area- and energy-efficient level shifter (LS) with wide voltage and frequency ranges. The proposed LS removes the static current with a cut-off head PMOS. The LS also provides a robust internal node compared to other state-of-the-art LSs, where the internal node is floated. To reduce the delay and energy consumption in the proposed LS, the contention between the pull-up and pull-down networks at the internal node is reduced by using a 'low' to 'high' transition error correction circuit (LtH ECC), which also enables high frequency operation at near- and sub-threshold voltages. The proposed LS is implemented in 65 nm CMOS technology, having the smallest area of 6.90 mu m(2) among state-of-art LSs. The measurement results demonstrate that the minimum low-level supply voltage (V-DDL,V-MIN) values are 120 mV and 300 mV with input frequency (f(IN)) of 1 MHz and 100 MHz, respectively, at a high-level supply voltage of 1.2 V. The delay and energy consumption at V-DDL of 120 mV and 300 mV are 207 ns and 1040 fJ, and 3.26 ns and 31.25 fJ, respectively. The static power consumption is less than 3 nW at V-DDL ranging from 120 mV to 700 mV.