Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

被引：25

作者：

Yu, X. R. ^{[1
]}

Chuang, M. H. ^{[2
]}

Chang, S. W. ^{[1
,3
]}

Chang, W. H. ^{[4
]}

Hong, T. C. ^{[3
,5
]}

Chiang, C. H. ^{[2
]}

Lu, W. H. ^{[1
]}

Yang, C. Y. ^{[1
]}

Chen, W. J. ^{[1
]}

Lin, J. H. ^{[6
]}

Wu, P. H. ^{[6
]}

Sun, T. C. ^{[1
]}

Kola, S. ^{[2
]}

Yang, Y. S. ^{[2
]}

Da, Yun ^{[2
]}

Sung, P. J. ^{[3
]}

Wu, C. T. ^{[3
]}

Cho, T. C. ^{[3
]}

Luo, G. L. ^{[3
]}

Kao, K. H. ^{[1
]}

Chiang, M. H. ^{[1
]}

Ma, W. C. Y. ^{[6
]}

Su, C. J. ^{[3
]}

Chao, T. S. ^{[5
]}

Maeda, T. ^{[4
]}

Samukawa, S. ^{[2
]}

Li, Y. ^{[2
]}

Lee, Y. J. ^{[3
,7
,8
]}

Wu, W. F. ^{[3
]}

Tarng, J. H. ^{[2
]}

Wang, Y. H. ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan, Taiwan

[2] Natl Yang Ming Chiao Tung Univ, Coll Elect & Comp Engn, Hsinchu, Taiwan

[3] Taiwan Semicond Res Inst TSRI, Hsinchu, Taiwan

[4] Natl Inst Adv Ind Sci & Technol, Tsukuba, Ibaraki, Japan

[5] Natl Yang Ming Chiao Tung Univ, Dept Elect, Hsinchu, Taiwan

[6] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung, Taiwan

[7] Natl Yang Ming Chiao Tung Univ, Inst Pioneer Semicond Innovat, Hsinchu, Taiwan

[8] Natl Univ Kaohsiung, Dept Elect Engn, Kaohsiung, Taiwan

来源：

2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM | 2022年

关键词：

D O I：

10.1109/IEDM45625.2022.10019507

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42% area reduction.

引用

页数：4

共 1 条

[1] Virtual Fab Coupled Physics-Based Simulation Design of sub-2nm Node 3D Heterogeneous Si/IGZO 6T SRAM
Di, Zhaohai
Zhao, Yue
Luo, Yanna
Xu, Haoqing
Wang, Lingfei
Bu, Jianhui
Li, Yongliang
Wu, Zhenhua
2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024, 2024, : 69 - 73

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