Low-power on-chip bus architecture using dynamic relative delays

被引：0
|
作者：
Ghoneima, M [1 ]
Ismail, Y [1 ]
机构：
[1] Northwestern Univ, ECE Dept, Evanston, IL 60201 USA
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/SOCC.2004.1362419
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a dynamic delayed line bus scheme (DDL) for low-power on-chip buses. This scheme dynamically introduces a delay to bus lines having a certain switching activity to create relative delay between opposite switching adjacent lines. The optimum relative delay introduced by this proposed scheme is shown to reduce the power dissipation by up to 16%.
引用
收藏
页码：233 / 236
页数：4
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