Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream

被引：8

作者：

Kowalczyk, Marcin ^{[1
]}

Ciarach, Piotr ^{[1
]}

Przewlocka-Rus, Dominika ^{[1
]}

Szolc, Hubert ^{[1
]}

Kryjak, Tomasz ^{[1
]}

机构：

[1] AGH Univ Sci & Technol, Dept Automat Control & Robot, Comp Vis Lab, Embedded Vis Syst Grp, Al Mickiewicza 30, PL-30059 Krakow, Poland

来源：

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2021年 / 93卷 / 05期

关键词：

FPGA; Zynq UltraScale plus MPSoC; 4K; UHD; Real-time video processing; Connected component labelling (CCA); Connected component analysis (CCA);

D O I：

10.1007/s11265-021-01636-4

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a hardware implementation in reconfigurable logic of a single-pass connected component labelling (CCL) and connected component analysis (CCA) module is presented. The main novelty of the design is the support of a video stream in 2 and 4 pixel per clock format (2 and 4 ppc) and real-time processing of 4K/UHD video stream (3840 x 2160 pixels) at 60 frames per second. We discuss several approaches to the issue and present in detail the selected ones. The proposed module was verified in an exemplary application - skin colour areas segmentation - on the ZCU 102 and ZCU 104 evaluation boards equipped with Xilinx Zynq UltraScale+ MPSoC devices.

引用

页码：481 / 498

页数：18

共 50 条

[1] Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream
Marcin Kowalczyk
Piotr Ciarach
Dominika Przewlocka-Rus
Hubert Szolc
Tomasz Kryjak
[J]. Journal of Signal Processing Systems, 2021, 93 : 481 - 498
[2] A comparison of real-time 4K/UltraHD connected component labelling architectures
Kowalczyk, Marcin
Kryjak, Tomasz
[J]. 2021 31ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2021), 2021, : 401 - 401
[3] Real-Time CLAHE Algorithm Implementation in SoC FPGA Device for 4K UHD Video Stream
Kryjak, Tomasz
Blachut, Krzysztof
Szolc, Hubert
Wasala, Mateusz
[J]. ELECTRONICS, 2022, 11 (14)
[4] Real-Time FPGA Implementation of the Semi-global Matching Stereo Vision Algorithm for a 4K/UHD Video Stream
Grabowski, Mariusz
Kryjak, Tomasz
[J]. DESIGN AND ARCHITECTURE FOR SIGNAL AND IMAGE PROCESSING, DASIP 2023, 2023, 13879 : 70 - 81
[5] An FPGA Implementation of Multi-channel Video Processing and 4K Real-Time Display System
Guo, Xin
Wei, Xinyue
Liu, Yiqing
[J]. 2017 10TH INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, BIOMEDICAL ENGINEERING AND INFORMATICS (CISP-BMEI), 2017,
[6] A Highly Parallel 4K Real-Time HEVC Fractional Motion Estimation Architecture for FPGA Implementation
Soto Leon, Jorge
Silva Cardenas, Carlos
Villegas Castillo, Ernesto Cristopher
[J]. 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 2016, : 708 - 711
[7] Implementation of Real-time Connected Component Labeling using FPGA
Tsai, Tsung-Han
Ho, Yuan-Chen
Tsai, Chi-En
[J]. 2018 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-TAIWAN (ICCE-TW), 2018,
[8] 4K Real-Time HEVC Decoder on an FPGA
Abeydeera, Maleen
Karunaratne, Manupa
Karunaratne, Geethan
De Silva, Kalana
Pasqual, Ajith
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2016, 26 (01) : 236 - 249
[9] Real-time implementation of adaptive correlation filter tracking for 4K video stream in Zynq UltraScale plus MPSoC
Kowalczyk, Marcin
Przewlocka, Dominika
Kryjak, Tomasz
[J]. 2019 CONFERENCE ON DESIGN AND ARCHITECTURES FOR SIGNAL AND IMAGE PROCESSING (DASIP), 2019, : 53 - 58
[10] Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale plus MPSoC
Kowalczyk, Marcin
Przewlocka, Dominika
Kryjak, Tomasz
[J]. 2018 CONFERENCE ON DESIGN AND ARCHITECTURES FOR SIGNAL AND IMAGE PROCESSING (DASIP), 2018, : 37 - 42

← 1 2 3 4 5 →