Design methodology of the embedded DRAM with the virtual socket architecture

被引：1

作者：

Kinoshita, M ^{[1
]}

Yamauchi, T ^{[1
]}

Amano, T ^{[1
]}

Dosaka, K ^{[1
]}

Arimoto, K ^{[1
]}

机构：

[1] Mitsubishi Elect Corp, ULSI Dev Ctr, Itami, Hyogo 6648641, Japan

来源：

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2000年

关键词：

D O I：

10.1109/CICC.2000.852664

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes the virtual socket architecture in order to reduce the design turn around time (TAT) of the embedded DRAM. By using the proposed architecture, the DRAM control circuitry is provided as the software macro to take advantage of the automated tools based on the synchronous circuit design. With array generator technology,this architecture can achieve high quality, quick turn around time (QTAT) flexible eDRAM design almost same as the CMOS ASIC. We applied this virtual socket architecture to the 0.18um embedded DRAM test device and confirmed over 166MHz operation.

引用

页码：271 / 274

页数：4

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