Pipelined ALU for signal processing to implement interval arithmetic

There are many applications within digital signal processing (DSP) that require the user to know how various numerical errors (uncertainty) affect the result. This uncertainty is represented by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors ate needed to implement interval arithmetic. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. We have proposed a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multiplication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruction. Division traditionally is not implemented on digital signal processors unless computed with a shift operation. In this design, division by shifting is implemented. The ALU is designed to have maximum throughput while minimizing area.