FPGA Implementation and Detection of a Simple Vowel-like Speech Algorithm

Vowel-like speech (VLS) is more speaker-specific and less degraded in noisy speech signals. Consequently, robust speech-based applications can be developed by means of VLS detection. From the various front-end speech parameterization methods documented in previous works for the detection of VLS, the extracted feature from the output of the zero-frequency filter (ZFF) of speech signal gives a better result. Features based on ZFF are relatively strong to the noises present in the environments. In the existing ZFF based VLS detection methods, the ZFF speech signal feature is further processed through very complex algorithms for detecting VLS. In this proposed approach, the extracted excitation strength (ES) of the ZFF speech signal is non-linearly mapped (NLM) at each time instant to enhance the discrimination of VLS in the speech signal. The NLM-ES values are significantly less in magnitude for VLS when compared to non-VLS. The regions where the NLM-ES values attain significantly lower magnitude are hypothesized as the VLS. The outcomes from the experiment of the present work indicate that VLS detection by this proposed method performs better than existing ZFF methods carried out earlier in clear and degraded signals. The hardware of the architecture is configured and verified for the present work by using field-programmable gate array (FPGA) implementations.