Inductorless SiGe BiCMOS Optical Receiver Front End for 25 Gb/s Optical Links

A novel inductorless optical receiver analog front end (AFE) design is demonstrated to require less chip area and is suitable for both low cost and high-speed optical communication applications. The optimized transimpedance amplifier (TIA) has a differential regulated cascode (RGC) topology, with a novel zero-pole canceling technique. The proposed limiting amplifier (LA) using Cherry-Hooper topology and negative Miller capacitance broaden the bandwidth. Based on the IBM 7WL 0.18 mu m SiGe BiCMOS process, the post-simulation results show a total transimpedance gain of 107.1 dB Omega and -3 dB bandwidth of 17 GHz. The chip consumes 132 mW power dissipation from a single 3.3 V supply and occupies the core area of only 110 x 340 mu m(2).