A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology

被引：0

作者：

Li, Miao ^{[1
]}

Kwasniewski, Tad ^{[1
]}

Wang, Shoujun ^{[1
]}

Tao, Yuming ^{[1
]}

机构：

[1] Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada

来源：

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18 mu m CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.

引用

页码：679 / 682

页数：4

共 50 条

[1] A 10Gb/s 10mW 2-Tap Reconfigurable Pre-Emphasis Transmitter in 65nm LP CMOS
Lu, Yue
Jung, Kwangmo
Hidaka, Yasuo
Alon, Elad
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
[2] A reduced power 6-tap pre-emphasis for 10Gb/s backplane communications
Cheng, Dezhong
Liang, Bangli
Chen, Dianyong
Kwasniewski, Tad
2008 24TH BIENNIAL SYMPOSIUM ON COMMUNICATIONS, 2008, : 93 - 96
[3] A 10Gb/s combined equalizer in 0.18μm CMOS technology for backplane communication
张明科
Hu Qingsheng
HighTechnologyLetters, 2015, 21 (02) : 205 - 211
[4] Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS
Goosen, Marius
Sinha, Saurabh
MICROELECTRONICS JOURNAL, 2011, 42 (11) : 1216 - 1224
[5] A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter
Farjad-Rad, R
Yang, CKK
Horowitz, MA
Lee, TH
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (05) : 580 - 585
[6] A 0.18 μm CMOS multi-Gb/s 10-PAM transmitter
Jeong, Jikyung
Lee, Jeongjun
Burm, Jinwook
PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009), 2009, : 516 - 519
[7] A fully on-chip 10Gb/s CDR in a standard 0.18 μm CMOS technology
Li, Jinghua
Silva-Martinez, Jose
2007 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2007, : 237 - +
[8] 10Gb/s limiting amplifier and laser/modulator driver in 0.18μm CMOS technology
Galal, S
Razavi, B
2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS, 2003, 46 : 188 - +
[9] A 1.6Gb/s CMOS LVDS Transmitter with a Programmable Pre-Emphasis System
Reyes, Benjamin T.
Paulina, German
Tealdi, Lucas
Labat, Emanuel
Sanchez, Raul
Mandolesi, Pablo S.
Hueda, Mario R.
2014 IEEE 5TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS), 2014,
[10] A Gated VCO for 10Gb/s PON Systems in 0.18μm CMOS
Gu, Gaowei
Zhu, En
Lin, Ye
SECOND INTERNATIONAL CONFERENCE ON FUTURE NETWORKS: ICFN 2010, 2010, : 261 - 264

← 1 2 3 4 5 →