The use of commercial-of-the-shelf SRAM-based FPGA devices in space applications is not yet a reality due to concerns still existing about the device reliability; therefore, more conservative approaches based on anti-fuse FPGAs are currently preferred. The major concern about the use of such devices in space stems from their sensitivity to ionizing radiation, which may alter the content of the design the device implements, and which forces to adopt error mitigation techniques that have very high resource overheads. In this paper we analyze a realistic case study taken front a future space mission, and we show how mitigation techniques that combine hardware and software redundancy can provide very good fault tolerance capabilities to designs that include processor cores, while reducing significantly the overhead of the mitigation technique with respect to the hardware redundancy approach that is nowadays used.