A new bulk-driven input stage design for sub 1-volt CMOS op-amps

被引：0
|
作者：
Haga, Yasutaka [1 ]
Morling, Richard C. S.
Kale, Izzet
机构：
[1] Univ Westminster, Dept Elect Syst, Appl DSP & VLSI Res Grp, London W1R 8AL, England
[2] Eastern Mediterranean Univ, Appl DSP & VLSI Res Ctr, Gazimagusa, New Zealand
来源：
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V(T0)+3V(DSsat)) to the maximum allowed for the CMOS process, as well as preventing latch-up.
引用
收藏
页码：1547 / 1550
页数：4
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