Crosstalk-aware TSV-buffer Insertion in 3D IC

3D integration is one of the promising technologies to alleviate interconnection delay. Implementing 3D IC is to integrate 2D ICs with Through-Silicon Vias (TSVs). For yield consideration, TSVs are bundled together as a TSV block [1]. Regrettably, this placement will result in crosstalk coupling noises in TSV block, which may cause significant timing degradation. Traditionally; buffer sizing is one of the effective methods to solve the problem. However, we have observed that increasing the TSV-buffer size of aggressor TSV will cause serious timing degradation to the victim TSV in 3D than wires in 2D cases. In this paper, we develop a delay model of a victim TSV surrounded by aggressor TSVs with different driving TSV-buffer sizes. Based on the TSV delay model, we propose (1) an ILP (Integer Linear Programming) method, which is able to find the near-optimal solution, and (2) an efficient crosstalk-aware heuristic method for practical use. Our experimental results show that the proposed heuristic method only uses 2.56% (3.05%) more TSV-buffers compared to the optimal ILP solution and achieves on average 32.88% (42.40%) and 18.21% (23.06%) area reduction of area-overheads compared to the conventional greedy [2] and separator sets [3] methods in our 2-tier (4-tier) benchmark circuits.