Low-power digital neuron for SOM implementations

A digital implementation of the self-organising map is shown to have reduced power requirements through a strategy of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs requiring two clock cycles, one clock cycle, and half clock cycle per element of the input vector have been constructed and analysed. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%.