Reduced Common Mode Voltage PWM Techniques for Dual Inverter Configuration

被引：0

作者：

Reddy, M. Harsha Vardhan ^{[1
]}

Reddy, T. Bramhananda ^{[1
]}

Reddy, B. Ravindranath ^{[2
]}

Kalavathi, M. Surya ^{[2
]}

机构：

[1] G Pulla Reddy Engn Coll Autonomous, Dept EEE, Kurnool, Andhra Pradesh, India

[2] JNTUH, Dept EEE, Hyderabad, Andhra Pradesh, India

来源：

2014 RECENT ADVANCES AND INNOVATIONS IN ENGINEERING (ICRAIE) | 2014年

关键词：

AZSPWM; Common mode voltage; Dual Inverter; NSPWM; SVPWM; 5-LEVEL INVERTER;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this paper a generalized scalar PWM algorithm for dual inverter configuration is presented. With the freedom provided by the PWM algorithms to choose zero sequence signal and carrier signals different PWM techniques for reducing common mode voltages are presented. In these PWM techniques the zero sequence signal is selected based on reference phase voltages and carrier signals are selected based on slope and region of location of reference signal. With proposed AZSPWM algorithms common mode voltages are reduced in dual inverter configuration and NSPWM algorithm reduces switching losses along with common mode voltage. With the proposed scalar approach the complexity involved in generating switching instants are greatly reduced when compared with space vector approach. To validate the theoretical concepts MATLAB based simulation studies are carried.

引用

页数：5

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