A marvelous low on-resistance 20V rated Self Alignment Trench MOSFET (SAT-MOS) in a 0.35μm LSI design rule with both high forward blocking voltage yield and large current capability

in this paper, we propose the SAT-MOS, which achieved marvelous performance of the Specific on-resistance (Ron, sp): 6.5mOmegamm(2) (@Vdss=30.8V) by minimizing the unit cell pitch but not too small (Fig.4) on a 0.35mum LSI design rule. This is the lowest value of 20V rated MOSFETs ever been reported. The fabricated SAT-MOS's Ron,sp ratio to the Si limit reaches the ultimate value 208% in this voltage class (Fig.1). An yield of a forward blocking voltage characteristics (Vdss) is so sensitive for the uniformity of the shallow source trench depth on a large size wafer to maintain as acceptable value for the mass-production without any special care to obtain an N and P common contact in a shallow p-base region accurately. We could solve this trade-off problem between minimizing a unit cell to reduce a Ron and a Vdss yield stability in a "Dual trench process" on the 0.35mum fine design rule by optimizing the Self-Alignment shallow trench Contact (SAC) ion implantation. So, the SAT-MOS maintains an excellent Vdss uniformity on a wafer, because our proposed SAC structure and procedure has a very large process window for SAC trench depth if the source contact trench depth disperses more than 20%. As a result, we could present the SAT-MOS, which has both a large current capability of over 100A/mm(2) in a static forward bias condition and an avalanche ruggedness of over 25A/mm(2) during unclamped inductive switching (UIS).