Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz

被引：1

作者：

Chu, Wei ^{[1
]}

Chen, Wei-Hao ^{[1
]}

Huang, Shi-Yu ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Elect Engn Dept, Hsinchu, Taiwan

来源：

2020 IEEE 38TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2020) | 2020年

关键词：

Delay-Locked Loop; Duty-Cycle Correction; Cell-Based Design; Tunable Delay Line; Fine Tuning; Zero Phase Shift; PLL;

D O I：

10.1109/ICCD50377.2020.00083

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a cell-based 50% Duty-Cycle Correction (DCC) design supporting a super-wide range of clock frequency from 10MHz to 1.2GHz, using a 90nm CMOS process. It can be integrated with a Delay-Locked Loop (DLL) as a convenient post-processing unit while achieving "zero phase shift" in a way that the phase locking result achieved by its precedent DLL is not affected at all. The unique features in this design include: (1) A wide-range and high-resolution Half-Period Tunable Delay Line (HP-TLD), (2) A fast-locking unit to enable our DCC to lock in to a new incoming clock frequency during frequency scaling, and (3) A wide-range and high-resolution Duty-Cycle Judge (DCJ) circuit as a feedback to guide the overall duty-cycle correction process. Post-layout simulation in a 90nm CMOS process is conducted to validate its effectiveness.

引用

页码：457 / 460

页数：4

共 22 条

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