Turbo decoding on the TMS320C6416 digital signal processor

Channel coding plays a crucial role in modern communication systems. Forward error correcting (FEC) channel codes provide improvements in the bit error rate performance by mitigating channel perturbations. Turbo codes approach the Shannon limit closer than other FEC codes. In this paper, the error performance of a turbo coded system has been analysed on a digital signal processor (DSP). By using a 720 MHz Spectrum Digital TMS320C6416 DSP Starter Kit (DSK), the error performance curves and coding gains of a 3GPP turbo coded system are obtained in an additive white Gaussian noise (AWGN) channel for different interleaver sizes. In the receiver, the on-chip Turbo decoder Co-Processor (TCP) of the DSP has been employed for decoding.