<bold>Full wafer integration of NEMS on CMOS by nanostencil lithography</bold>

被引：0

作者：

Arcamone, Julien ^{[1
]}

van den Boogaart, Marc A. F. ^{[2
]}

Serra-Graells, Francesc ^{[1
]}

Hansen, Sven ^{[3
]}

Brugger, Juergen ^{[2
]}

Torres, Francesc ^{[4
]}

Abadal, Gabriel ^{[4
]}

Barniol, Nuria ^{[4
]}

Perez-Murano, Francesc ^{[1
]}

机构：

[1] CSIC, CNM IMB, Campus UAB, E-08193 Barcelona, Spain

[2] Ecole Polytech Fed Lausanne, Microsyst Lab, CH-1015 Lausanne, Switzerland

[3] SUSS MicroTec Lithog GmbH, D-85748 Garching, Germany

[4] Autonomous Univ Barcelona, Dept Enginyeria Elect, E-08193 Bellaterra, Spain

来源：

2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Wafer scale nanostencil lithography is used to define 200 rim scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of similar to 2000 nano-devices by post-processing standard CMOS wafers using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies around 1.5 MHz were measured in air and vacuum and tuned by applying dc voltages of 10V and 1V respectively.

引用

页码：250 / +

页数：2

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