Redundant adders consume less energy

We conduct a complete analysis of the effect of digit redundancy in adders on their delay, power, energy, and energy-delay product. To our knowledge, this is the first such detailed analysis. We discuss the hybrid signed digit representations that offer a continuum of choices from two's complement representation on one extreme, all the way to a fully signed digit representation on the other extreme. Power and time delay reductions are achieved as a result of algorithmic level changes. Our analysis using TSMC 1.8 mu m technology indicates that the increment in power over the whole range from two's complement to fully signed representation is relatively small (52-174%), while the reduction in speed is much larger (95.455%). The best designs from the energy and energy-delay product points of view are the most redundant. We also present a new Modified Hybrid Signed Digit(MHSD) adder that leads to greater improvements. Compared to the Hybrid Signed Digit(HSD) adder [1], MHSD adder shows power decrement of 1.653% and speed increment of 17.716%.