Development of low-power and real-time VC-1/H.264/MPEG-4 video processing hardware

被引：0

作者：

Hase, Masaru ^{[1
]}

Akie, Kazushi ^{[1
]}

Nobori, Masaki ^{[1
]}

Matsumoto, Keisuke ^{[1
]}

机构：

[1] Renesas Technol Corp, Syst Design Dept 3, Syst Design Div, Syst Solut Business Grp, Tokyo, Japan

来源：

PROCEEDINGS OF THE ASP-DAC 2007 | 2007年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper covers a multi-functional hardware intellectual property (IP) for the encoding and decoding of digital moving pictures with low power consumption. The IP is mainly intended for mobile products such as cellular phones, digital still cameras (DSCs), and digital video cameras (DVCs). It includes VC-1 functionality for Internet content plus AVC (H.264) functionality for digital television broadcasting and MPEG-4 functionality for TV telephony, and is capable of processing D1-sized moving pictures (720 pixels by 480 lines) in real time at an operating frequency of 54 MHz. In addition, original algorithms employed in the IP reduce power consumption by up to 22%.

引用

页码：637 / +

页数：3

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