A CMOS dual-band tri-mode chipset for IEEE 802.11a/b/g wireless LAN

被引：22

作者：

Mehta, S ^{[1
]}

Zargari, M ^{[1
]}

Jen, S ^{[1
]}

Kaczynski, B ^{[1
]}

Lee, M ^{[1
]}

Mack, M ^{[1
]}

Mendis, S ^{[1
]}

Onodera, K ^{[1
]}

Samavati, H ^{[1
]}

Si, W ^{[1
]}

Singh, K ^{[1
]}

Terrovitis, M ^{[1
]}

Weber, D ^{[1
]}

Su, D ^{[1
]}

机构：

[1] Atheros Commun, Sunnyvale, CA 94085 USA

来源：

2003 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2003年

关键词：

D O I：

10.1109/RFIC.2003.1213977

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of a dual-band, tri-mode wireless LAN chipset for IEEE 802.11a/b/g. The chipset, designed in 0.25mum standard CMOS, features a 5GHz RF transceiver, a 2.4GHz RF transceiver, and a base-band processor with media access controller. The overall design achieves a measured sensitivity of at least -70dBm at 54Mbps and -92dBm at 6Mbps for IEEE 802.11a/g as well as -94dBm at 1Mbps for 802.11b.

引用

页码：427 / 430

页数：4

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