A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters

被引：7
|
作者：
Lin, Jian-He [1 ]
Yang, Shang-Hsien [1 ]
Muniandi, Balakumar [1 ]
Ma, Yu-Sheng [1 ]
Huang, Chia-Ming [1 ]
Chen, Ke-Horng [1 ]
Lin, Ying-Hsi [2 ]
Lin, Shian-Ru [2 ]
Tsai, Tsung-Yen [2 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect & Comp Engn, Hsinchu 300, Taiwan
[2] Realtek Semicond Corp, Hsinchu 300, Taiwan
来源：
IEEE TRANSACTIONS ON POWER ELECTRONICS | 2020年 / 35卷 / 04期
关键词：
Regulators; Switches; Voltage control; Transient analysis; Switching frequency; Transient response; Digital low-dropout regulator (DLDO); nonlinear switch control (NLSC) technique; power-saving mode; variable switching frequency control; LDO; PERFORMANCE; MANAGEMENT; VOLTAGE; CMOS;
D O I：
10.1109/TPEL.2019.2939415
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 A and reduces the switching power loss through variable switching frequency control. With a load step of 1-20mA, the transient response time is 1.3 s and the peak current efficiency is 99.8 at heavy loads.
引用
收藏
页码：3997 / 4008
页数：12
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