High Voltage I/O FinFET Device Optimization for 16nm System-on-a-Chip (SoC) Technology

被引：0

作者：

Miyashita, T. ^{[1
]}

Kwong, K. C. ^{[1
]}

Wu, P. H. ^{[1
]}

Hsu, B. C. ^{[1
]}

Chen, P. N. ^{[1
]}

Tsai, C. H. ^{[1
]}

Chiang, M. C. ^{[1
]}

Lin, C. Y. ^{[1
]}

Wu, S. Y. ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co Ltd, 168,Pk Ave 2,Hsinchu Sci Pk, Hsinchu, Taiwan

来源：

2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

High voltage I/O FinFET device optimization for a 16nm system-on-a-chip (SoC) technology is presented. After careful optimization through high electric field (E-field) mitigation by junction engineering, I/O FinFET devices with leakage current reduction by 1 similar to 2 orders, hot carrier injection (HCI) lifetime improvement by 2.8x/1.2x for N- and PMOS, respectively, and junction breakdown voltage (V-bd) improvement by more than 0.8V are achieved.

引用

页数：2

共 29 条

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