(1/3) x VDD-to-(3/2) x VDD Wide-Range I/O Buffer Using 0.35-μm 3.3-V CMOS Technology

被引：6

作者：

Huang, Chi-Chun ^{[1
]}

Lee, Tzung-Je ^{[1
]}

Chang, Wei-Chih ^{[1
]}

Wang, Chua-Chin ^{[1
]}

机构：

[1] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung 80424, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2010年 / 57卷 / 02期

关键词：

Floating n-well; gate tracking; input/output (I/O) buffer; level converter; mixed-voltage tolerant; VOLTAGE OUTPUT DRIVER; DESIGN;

D O I：

10.1109/TCSII.2010.2040311

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 0.9/1.2/1.8/2.5/3.3/5.0-V wide-range input/output buffer carried out using a typical complementary metal-oxide semiconductor (MOS) 2P4M 0.35-mu m process is proposed in this brief. An input buffer with a logic calibration circuit is used for receiving a low voltage signal. A novel floating n-well circuit is employed to remove the body effect at the output p-channel MOS (PMOS). Moreover, a dynamic driving detector is included to equalize the turn-on voltages for the output PMOS and n-channel MOS transistors. The worst-case duty cycle of the output signal can then be 54.2% in a low-voltage mode. The maximum output frequency of the proposed design is measured to be 17.9/27.9/35.3/70.1/79.2/60.0 MHz for VDDIO = 0.9/1.2/1.8/2.5/3.3/5.0 V, respectively. The power consumption is 553 nW at the worst simulation case of [SS, 100 degrees C] and 330 nW by on-silicon measurement.

引用

页码：126 / 130

页数：5

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