Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V-D = 1.8 V. We present a comprehensive study on the I-V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0-7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET (V-thn) of between 0.70 and 0.72 V and a saturation current (I-DSAT) of between 280 and 300 muA/mum, thick oxide nMOSFET have a V-thn of between 0.85 and 0.90 V and an I-DSAT of between 160 and 200 muA/mum in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V-g = 8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power. (C) 2003 Elsevier Science Ltd. All rights reserved.