50MHz data acquisition system based on virtual instrument

This paper provides a new mode of developing virtual instrument. High-speed devices cooperated with CPLD are utilized to accomplish the data acquisition process. The measured signals are sampled by high-speed A/D converter and reserved by first-in first-out FIFO memory. Both of them work under a clock higher than 50MHz and the speed of FIFO should be higher than A/D. Sequential logic generated by CPLD is employed to control and manage the whole course of data acquisition. It contains 5 modules: communicate, time sequence control, core state control, memory proportion control and trigger control. Then data in FIFO are conveyed to software in PC through USB bus. Microprocessor controls the whole data acquisition system: on the one hand, it operates the USB interface to communicate with PC, responds orders from PC and conveys data to PC; on the other hand, it visits registers in CPLD, manipulates the process of data acquisition. Experimental results indicate that this mode of virtual instrument is valid and reliable; the sampling frequency can reach 50MHz.