Optimum Number of Cascaded Cells for High-Power Medium-Voltage Multilevel Converters

When power electronic systems are connected to the medium-voltage grid, often multilevel topologies consisting of a number of cascaded converter cells are considered. For a given grid voltage level, either few cells featuring semiconductors with high blocking voltage capability or many cells using low-voltage semiconductors can be employed. This paper proposes efficiency/power density (eta-rho) Pareto analysis to comprehensively identify the optimum number of cascaded cells. Recent advances in silicon carbide (SiC) semiconductor technology point towards devices with blocking voltages exceeding 15 kV. The switching characteristics that hypothetical SiC devices would have to provide in order to realize a simple single-stage full-bridge converter competitive to a multilevel solution are derived and found to be impracticably fast. Furthermore, it is shown that reliability concerns arising with increasing number of cascaded cells can be mitigated by means of redundancy.