Logical Effort using a Novel Discrete Particle Swarm Optimization Algorithm

Designers often need to choose the gate sizes for logic circuit designs to estimate the delay of the circuit. Simulation and timing analysis are poor tools for this task because they cannot be modified for better results. Hence, the method of Logical Effort (LE) provides a simple method to overcome these design problems. We apply a novel Discrete Particle Swarm Optimization algorithm (DPSO) to solve the LE problem for electronic circuits. The method uses the rescaling function commonly used to scale datasets in neural networks to convert continuous-valued PSO values into discrete values. The proposed algorithm was successfully applied on a three-stage NAND gate circuit, and has been shown to work well, with 100% accuracy in all test runs.