A Compensation Technique for Threshold Mismatch in Sub-threshold Current Mirror

A novel compensation method is proposed to eliminate the threshold mismatch in sub-threshold current mirror. The gate voltage of transistor pair in basic current mirror is modified through negative feedback loop during tuning phase, thereby compensates the threshold variation from imperfect fabrication process. The circuit is implemented and simulated with 1.8V supply using standard 0.18 mu m CMOS technology and it accomplishes less than 1% inaccuracy with +/- 5% threshold variation in the 500nA input current range. The presented approach provides an accurate and continuous current copy in a wide current range while still preserving the original structure of transistor pair, which means this technique can be implemented in various current mirror design without affecting its input and output characteristic.