A 2-D systolic array for high-throughput computation of 2-D discrete fourier transform

被引：0
|
作者：
Meher, P. K. [1 ]
Patra, J. C. [1 ]
Vinod, A. P. [1 ]
机构：
[1] Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore
来源：
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年
关键词：
discrete Fourier transform (DFT); systolic array; digital signal processing (DSP) chip; VLSI;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A simple 2-dimensional architecture is derived for highly concurrent systolization of the 2-dimensional (2-D) discrete Fourier transform (DFT). The concurrency of computation has been enhanced and complexity is minimized by the proposed algorithm where an N-point DFT is computed via four inner-products of real-valued data of length approximate to (N/2). The proposed structure offers significantly lower latency, twice the throughput, and involves nearly the same area-time complexity of the existing multiplier-based DFT structures.
引用
收藏
页码：1927 / +
页数：3
相关论文
共 50 条
  • [1] Systolic Array Based VLSI Architecture For High Throughput 2-D Discrete Wavelet Transform
    Wang, Hongda
    Choy, Chiu-Sing
    2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2016, : 100 - 103
  • [2] A systolic array architecture for 2-D discrete Hartley transform
    Karimi, B
    Baradaran-seyed, T
    6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XIII, PROCEEDINGS: CONCEPTS AND APPLICATIONS OF SYSTEMICS, CYBERNETICS AND INFORMATICS III, 2002, : 434 - 440
  • [3] Design of array processors for 2-D Discrete Fourier Transform
    Peng, ST
    Sedukhin, I
    Sedukhin, S
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1997, E80D (04) : 455 - 465
  • [4] Highly concurrent reduced-complexity 2-D systolic array for discrete Fourier transform
    Meher, Pramod Kumar
    IEEE SIGNAL PROCESSING LETTERS, 2006, 13 (08) : 481 - 484
  • [5] Performance Analysis for 2-D Convolution Implemented with the 2-D Modified Discrete Fourier Transform
    Radhakrishnan, C.
    Jenkins, W. K.
    2012 CONFERENCE RECORD OF THE FORTY SIXTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS (ASILOMAR), 2012, : 835 - 839
  • [6] The 2-D Modulated Discrete Fourier Transform for 2-D Fast Convolution and Digital Filtering
    Radhakrishnan, C.
    Jenkins, W. K.
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 1508 - 1511
  • [7] 2-D Systolic Array architecture of CBNS based Discrete Hilbert Transform Processor
    Mukherjee, Madhumita
    Sanyal, Salil Kumar
    MICROPROCESSORS AND MICROSYSTEMS, 2021, 87 (87)
  • [8] NEW SYSTOLIC ARRAY IMPLEMENTATION OF THE 2-D DISCRETE COSINE TRANSFORM AND ITS INVERSE
    CHANG, YT
    WANG, CL
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1995, 5 (02) : 150 - 157
  • [9] ON COMPUTING 2-D SYSTOLIC ALGORITHM FOR DISCRETE COSINE TRANSFORM
    LEE, MH
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1990, 37 (10): : 1321 - 1323
  • [10] Systolic Architecture for Implementation of 2-D Discrete Sine Transform
    Murty, M. N.
    Nayak, S. S.
    Padhy, B.
    Panda, S. N.
    INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011, 2012, 30 : 441 - 448
12345