Pattern based prediction for plasma etch

Plasma etching is a key process for pattern formation in integrated circuit (IC) manufacturing. Unfortunately, pattern-dependent nonuniformities arise in plasma etching processes due to localized microloading and feature size or aspect ratio-dependent reactive ion etch lag. We propose a semi-empirical methodology for characterization and chip-scale modeling of pattern-dependent effects in plasma etching of ICs. We apply this methodology to the study of interconnect trench etching and show that an integrated model is able to predict both pattern density and feature size dependent nonuniformities in trench depth.